
From courtyb@cdfsun3.in2p3.fr Wed Jul 29 14:05:47 1998
Date: Thu, 25 Jun 1998 16:21:43 +0200 (MET DST)
From: Bernard Courty <courtyb@cdfsun3.in2p3.fr>
To: brunet@cdf.in2p3.fr, guglielmi@cdf.in2p3.fr, tristram@cdf.in2p3.fr

FRONT END BUFFERS AND TRIGGERS SIMULATION BOARD

This is a 5V board designed to test acquisition software in a
real-like situation. It is software controlled with 3 registers:


***COMMAND REGISTER: (active high) (write on CS4 of PPC403)

D0: TRIGGER ENABLED - Reset trigger counters and then activate triggers generation and counting.
D1: ReadAck - Trigger Read Acknoledge
D2: INITRD1 - initiate a read DMA request on channel 1
D3: INITWR1 - initiate a write DMA request on channel 1
D4: INITRD2 - initiate a read DMA request on channel 2
D5: INITWR2 - initiate a write DMA request on channel 2
D6: ENDWR1 - position channel 1 for read after the end of a write
D7: ENDWR2 - position channel 2 for read after the end of a write

This byte should be the Least Significant Byte of a 32 bits write access.

****TRIGGERS STATUS FIFO: (active high) (read on CS4 of PPC403 with MA3=0 addr=00)
On every high-to-low transition of EVTCLK* a status byte is written
in a FIFO. It should be read in a 32 bits read access (Low Significant Byte).

D0-D3: EVTSYNC 0-3 - 4 low significant bits of the EVTCLK counter.
D4: ISASLOW - this trigger is a slow event one.
D5: ISAFAST - this trigger is a fast event one.
D6: ISASEC - this trigger appended before the precedent was fully processed (before ReadAck)

D7: FIFOE - is not written in the FIFO with EVTCLK, it just means the FIFO is empty.

FIFOE is connected to a LED which should stay almost continiously enlighted as
a normal behaviour (no event lost).

***COUNT ALL TRIGGERS REGISTER: (read on CS4 of PPC403 with MA3=1 addr=08)
32 bits counter of all events arrived (generating EVTCLK or not)


Hardware features and signals:

- PM input generating random fast event triggers.
- an adjustable oscillator for slow event triggers.
- 2  32k x 32bits buffers for the 2 DMA channels (one for fast and one for slow event)
- 2 DMA channels control signals: DMARequest1-2, DMAAcknoledge1-2, and EndOfTransfert1-2.
- DMA common synchronisation signals: SYSCLK and DMADXFER.
- 32bits processor data bus.
- EVTSYNC 0..3
- EVTCLK*
- CSs and Addr bits needed. (e.g. CS4 and MA3)
- LEDs for fast events (red) and FIFOE (green).
- everything I have forgotten.


NOTE 1: on the Proto I the byte corresponding to COMMAND REGISTER and TRIGGERS STATUS FIFO
is the Most Significant Byte due to a bytes inversion. A correction for COUNTER is also needed.
NOTE 2 (obsolete) : addresses and CSs for this 3 accesses are to be discussed.

Bernard Courty - courtyb@cdf.in2p3.fr
PCC-College De France
25/06/98
